An integrated circuit contains a flash memory cell in which a top gate of the sense transistor is a metal plate over the floating gate. This flash cell may be integrated into a complementary metal oxide semiconductor (CMOS) fabrication flow with the addition of one extra photolithography operation. The top gate is formed by a wet etch process which undercuts the metal plate, requiring the floating gate to be oversized. Oversizing the floating gate may lead to reliability problems for the flash cell due to increased hot carrier injection. The oversized floating gate requires large lateral field for efficient hot carrier injection programming. For certain process, the required value is physically impossible to achieve. In order to enable efficient HCI programming at low drain voltage, for example less than 6 volt, the channel length must be reduced.